1. Field of the Invention
The invention relates in general to a reading circuitry in a memory, and more particularly to a reading circuitry in a memory performing read operation by sensing a source current from the source side of a memory cell.
2. Description of the Related Art
Memory devices have now been widely used in the field of data storage. A memory has many memory cells normally arranged in an array. Each row of memory cells corresponds to a word line, and each column of memory cells corresponds to a bit line. Each memory cell includes a transistor. The first end of the transistor is coupled to the bit line, the second end is coupled to the other bit line, and the control end is coupled to the corresponding word line.
Each memory cell defines a binary bit, that is, either of “0” and “1”. Normally, the programmed-bit represents “0”, and the erased bit represents “1”. Besides, in some forms of the memory, the memory cell stores two binary bits, that is, the first bit and the second bit. The first bit may represent “0” or “1”, and the second bit also may represent “0” or “1”.
Generally speaking, in a read operation mode, the memory determines the state of a memory cell by sensing the current received by the memory cell. Referring to FIG. 1, a circuit diagram of a conventional memory is shown. The memory 100 includes many memory cells and a memory read operation circuit 110. In FIG. 1, the memory cells are exemplified by a first memory cell M1 and a second memory cell M2 only, but is not limited thereto. The memory read operation circuit 110 includes a sensing selection circuit 112, a sensing circuit 113, a charging selection circuit 114 and a drain side bias circuit 115.
The first memory cell M1 is coupled to a first bit line BL1 and a second bit line BL2. The second memory cell M2 is coupled to the second bit line BL2 and a third bit line BL3. Both the first memory cell M1 and the second memory cell M2 are controlled by a word line WL. In a read operation mode, the second bit line BL2 is connected to the sensing circuit 113 by the sensing selection circuit 112. Besides, the first bit line BL1 is connected to the drain side bias circuit 115 by the charging selection circuit 114. That is, the first end of the first memory cell M1 has a drain voltage VD. The sensing circuit 113 senses the sensing current Isen flowing through the sensing selection circuit 112 to determine the state of the first memory cell M1. If the sensing current Isen is larger than a reference current Iref, then the first memory cell M1 is determined as “1”. If the sensing current Isen is smaller than reference current Iref, then the first memory cell M1 is determined as “0”.
Besides, in a read operation mode, the third bit line BL3 is floating and will be charged up by Ierr during senging operation. That is, the first memory cell M1 has a discharging current from the second memory cell M2.
However, when the first memory cell M1 represents “1” and the second memory cell M2 also represents “1”, there will be a leakage current, that is, the error current Ierr, flowing from the second end of the second memory cell M2 to the first end of the second memory cell M2. Under the above circumstances, the sensing current Isen does not equal to the drain current Id, reducing the reliability in the read operation of the memory 100, and deteriorating the overall performance of the memory 100.